1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices, and particularly to a method for fabricating a semiconductor device having silicide protection film.
2. Description of the Background Art
With transistors used for logic LSIs (Large-Scale Integrated Circuits), technology called salicide (self-aligned silicide) in which a silicide film is formed in a selective and self-aligned manner in the surface of a source/drain region and a polysilicon gate electrode in order to simultaneously reduce parasitic resistance of the source/drain region and interconnection resistance of the polysilicon gate electrode.
The salicide technology will now be described referring to FIG. 16 and FIG. 17.
First, as shown in FIG. 16, after formation of an MOS transistor M1 (in this case, N-channel type) on a silicon substrate SB, a metal film ML of cobalt (Co), for example, is formed by sputtering to a thickness of about 100 .ANG. on the surface of the source/drain region SD, the exposed surface of the polysilicon gate electrode GE, and on the surface of the sidewall oxide film SW.
Next, a thermal treatment is performed under a temperature condition of 400 to 500.degree. C. for 30 to 120 seconds to cause the part where the metal film MS and the silicon layer are in contact to react to form a silicide film. After that, the part remaining unreacted is removed by a wet etching and then a thermal treatment is applied under a temperature condition of 800 to 900.degree. C. for 30 to 120 sec, so that a silicide film SF is formed only on the surface of the source/drain region SD and on the exposed surface of the polysilicon gate electrode GE, as shown in FIG. 17.
While the silicide film has the advantage of reducing the parasitic resistance and the interconnection resistance as stated above, the formation of the silicide film may bring about undesirable phenomena. In this case, as a countermeasure, a silicide protection film for preventing the formation of the silicide film is formed in the part where the formation of the silicide film is undesirable.
Next, a problem raised by the formation of the silicide film, and the silicide protection film will be described. First, FIG.18 shows an inverter circuit C2 and a protection circuit C1 for protecting it as an example of a semiconductor integrated circuit.
The protection circuit C1 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected in series, with an input pad PD connected to the node ND1 connecting the two transistors. The P-channel MOS transistor P1 has its gate electrode connected to the power-supply potential (Vcc) and it is always kept in an OFF state. The N-channel MOS transistor N1 has its gate electrode connected to the ground potential and it is always kept in an OFF state.
The inverter circuit C2 includes a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected in series, with the connection node ND2 between the two connected to another circuit not shown. The gate electrodes of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 are connected to the node ND1 of the protection circuit C1.
Now, suppose that a surge voltage is inputted through the input pad PD, that is, that ESD (Electro Static Discharge) occurs. The surge voltage is much larger than the operating voltage of a common MOS transistor. In the absence of the protection circuit C1, the surge voltage will be applied to the gate electrodes of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 of the inverter circuit C2 to possibly dielectric breakdown the gate insulation of the two. However, in the presence of the protection circuit C1, an application of the surge voltage causes the source/drain of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 to break down to allow a current to flow, which prevents application of the surge voltage to the inverter circuit C2.
However, in the protection circuit C1, if an extremely large surge voltage is applied between the source and drain, the P-channel MOS transistor P1 or the N-channel MOS transistor N1 in the protection circuit C1 will destroy. The surge voltage at the time of destroy is called an ESD resistance, which is desirably set to a value as large as possible. However, if a silicide film is formed on the surface of the source/drain region, the ESD resistance voltage may be lowered.
FIG. 19 shows the structure of the MOS transistor M1 in a plane view. The MOS transistor M1 is formed of an elongate gate electrode GE provided in the center and a source/drain region SD on its both sides in the shorter direction, with a silicide film SF formed on the surface of the source/drain region SD.
FIG. 20 shows an enlarged view of the region A shown in FIG. 19. The silicide film SF generally has a polycrystal structure, which, as shown in FIG. 20, is formed of silicide crystal grains GR of various sizes. Accordingly, at grain boundaries, shapes of the individual grains are reflected to form undulations. The same is true at the edge portion of the silicide film SF along the edge portion of the gate electrode GE, and the crystal grains GR face each other with the gate electrode GE interposed therebetween, as shown in FIG. 20. When a surge voltage is applied to this structure, the surge current is concentrated to the part between protrusions of the crystal grains GR on both sides of the gate electrode GE (the part shown by the arrow) to intensively break that part, which deteriorates operation of the MOS transistor and destroys the function as a protection circuit. For this reason, a silicide film is not formed on the surface of the source/drain region in the protection circuit, and a silicide protection film is formed instead.
Next, referring to FIG. 21 and FIG. 22, the structure of an MOS transistor M2 having a silicide protection film will be described.
As shown in FIG. 21, a silicide protection film SP composed of a silicon oxide film (SiO.sub.2) is formed on the surface of the gate electrode GE and on the surface of the source/drain region SD in the vicinity of the gate electrode GE. FIG. 22 shows the cross section along the line A--A shown in FIG. 21.
As shown in FIG. 22, the silicide protection film SP is formed on the surface of the gate electrode GE and the sidewall oxide film SW, and on the surface of the source/drain region SD in the vicinity of the gate electrode GE, with no silicide film SF formed on the top of the silicide protection film SP. This structure enlarges the distance between the edge portions of the silicide film SF and the edge portions of the gate electrode GE. Hence, even if the edge portions of the silicide film SF are shaped in the form of continuous irregularities and the surge current is concentrated to protruding parts, the surge current passes through the highly resistive source/drain region SD and lightly-doped drain region LD so that the voltage is lowered. Furthermore, it diffuses since it travels in a long distance in the source/drain region SD and the lightly-doped drain region LD, so that the MOS transistor is prevented from destroy.
As described above, in MOS transistors in which formation of a silicide film SF causes troubles, a silicide protection film SP is formed to prevent the formation of the silicide film SF.
When forming the silicide protection film SP, a silicon oxide film is formed all over the surface of the silicon substrate SB and then the silicon oxide film is selectively removed by a dry etching to form the silicide protection film SP only on the surface of the gate electrode GE and the source/drain region SD in the vicinity of the gate electrode GE.
Accordingly, the surface of the silicon substrate SB is exposed not only to etching for formation of the sidewall oxide film SW of the MOS transistor but also to etching for formation of the silicide protection film SP. When an MOS transistor is formed on a bulk silicon substrate, removing the substrate surface to some extent with an increased number of etching processes causes no serious problem. However, when an MOS transistor is formed on an SOI substrate having a semiconductor layer formed in the form of a film on an insulating substrate, specifically an SOI (semiconductor-on-isolation) layer, the increased number of etching processes causes a serious problem.
FIG. 23 shows a structure in which a silicide protection film is formed on an MOS transistor M3 formed on an SOI substrate.
In FIG. 23, the SOI substrate SI includes a buried insulating layer BO formed on a silicon substrate SB and an SOI layer SL formed on the buried insulating layer BO. The MOS transistor M3 is formed on the SOI layer SL. Generally, the SOI layer SL is so thin that the influence of overetching cannot be neglected.
For example, FIG. 23 shows a step D1 at the edge portion of the sidewall oxide film SW, which is formed by over-etching when the sidewall oxide film SW is formed. The thickness of the SOI layer SL is reduced by the height of the step D1. At the edge portion of the silicide protection film SP, a step D2 is formed by overetching when forming the silicide protection film SP, which reduces the thickness of the SOI layer SL by its height. Thus the two times of overetching largely reduces the thickness of the SOI layer SL in the part uncovered by the silicide protection film SP. If a silicide film SF is formed in that part, the remaining SOI layer SL may all become the silicide film SF. In a part where the SOI layer SL is all formed of the silicide film SF, the inferior adhesion between the buried insulating layer BO (SiO.sub.2 layer) and the silicide film SF causes the silicide film SF to exfoliate to form conductive dust. If the conductive dust remains on the semiconductor device, it will adversely affect the operating characteristics of the semiconductor device. If the part to become a source/drain region becomes the silicide film SF and exfoliate, the original functions of the semiconductor device cannot be obtained.